$1C0C/7180/VIA2+12:   Peripheral Control Register

   +----------+-----------------------------------------------------+
   | Bits 7-5 |   CB2 Control:                                      |
   |          |     000 = Input negative active edge                |
   |          |     001 = Independent interrupt input negative edge |
   |          |     010 = Input positive active edge                |
   |          |     011 = Independent interrupt input positive edge |
   |          |     100 = Handshake output                          |
   |          |     101 = Pulse output                              |
   |          |     110 = Low output                                |
   |          |     111 = High output                               |
   | Bit  4   |   CB1 Interrupt Control: 0 = Negative active edge   |
   |          |                          1 = Positive active edge   |
   | Bit  3-1 |   CA2 Control: see Bits 7-5                         |
   | Bit  0   |   CA1 Interrupt Control: see Bit 4                  |
   +----------+-----------------------------------------------------+

   CA1 (Input):  BYTE-READY
   CA2 (Output): SOE (High = activate BYTE-READY)
   CB2 (Output): Head Mode (Low = Write, High = Read)

ROM-Reference:

 LDA $1C0C  : $F263 $F2B6 $F599 $F5CC $FABE $FDA3 $FE00 $FE0E
 STA $1C0C  : $F26C $F2BB $F5A0 $F5D1 $FAC3 $FDAA $FE05 $FE15