I/O Ports & Handshaking

I/O Ports (PRA, PRB, DDRA, DDRB)

Ports A and B each consist of an 8-bit Peripheral Data Register (PR) and an 8-bit Data Direction Register (DDR). If a bit in the DDR is set to a one, the corresponding bit in the PR is an output; if a DDR bit is set to a zero, the corresponding PR bit is defined as an input. On a READ, the PR reflects the information present on the actual port pins (PA0-PA7, PB0-PB7) for both input and output bits. Port A and Port B have passive pull-up devices as well as active pull-ups, providing both CMOS and TTL compatibility. Both ports have two TTL load drive capability. In addition to normal I/O operation, PB6 and PB7 also provide timer output functions.

REG	NAME	D₇	D₆	D₅	D₄	D₃	D₂	D₁	D₀
0	PRA	PA₇	PA₆	PA₅	PA₄	PA₃	PA₂	PA₁	PA₀
1	PRB	PB₇	PB₆	PB₅	PB₄	PB₃	PB₂	PB₁	PB₀
2	DDRA	DPA₇	DPA₆	DPA₅	DPA₄	DPA₃	DPA₂	DPA₁	DPA₀
3	DDRB	DPB₇	DPB₆	DPB₅	DPB₄	DPB₃	DPB₂	DPB₁	DPB₀

Handshaking

Handshaking on data transfers can be accomplished using the output pin and the input pin. PC will go low for one cycle following a read or write of PORT B. This signal can be used to indicate "data ready" at PORT B or "data accepted" from PORT B. Handshaking on 16-bit data transfers (using both PORT A and PORT B) is possible by always reading or writing PORT A first. is a negative edge sensitive input which can be used for receiving the output from another 6526, or as a general purpose interrupt input. Any negative transition of will set the interrupt bit.