6526 Interface Signals

INPUT CLOCK ()

The clock is a TTL compatible input used for internal device operation and as a timing reference for communicating with the system data bus.

CHIP SELECT ()

The input controls the activity of the 6526. A low level on while is high causes the device to respond to signals on the and address (RS) lines. A high on prevents these lines from controlling the 6526. The line is normally activated (low) at by the appropriate address combination.

READ/WRITE ()

The signal is normally supplied by the microprocessor and controls the direction of data transfers of the 6526. A high on indicates a read (data transfer out of the 6526), while a low indicates a write (data transfer into the 6526).

REGISTER SELECTS (RS3-RS0)

The address inputs select the internal registers as described by the Register Map:

RS3 RS2 RS1 RS0 REG
NAME
DESCRIPTION
0
0
0
0
0
PRA
  PERIPHERAL DATA REGISTER A
0
0
0
1
1
PRB
  PERIPHERAL DATA REGISTER B
0
0
1
0
2
DDRA
  DATA DIRECTION REGISTER A
0
0
1
1
3
DDRB
  DATA DIRECTION REGISTER B
0
1
0
0
4
TA LO
  TIMER A LOW REGISTER
0
1
0
1
5
TA HI
  TIMER A HIGH REGISTER
0
1
1
0
6
TB LO
  TIMER B LOW REGISTER
0
1
1
1
7
TB HI
  TIMER B HIGH REGISTER
1
0
0
0
8
TOD 10THS
  10THS OF SECONDS REGISTER
1
0
0
1
9
TOD SEC
  SECONDS REGISTER
1
0
1
0
A
TOD MIN
  MINUTES REGISTER
1
0
1
1
B
TOD HR
  HOURS -- AM/PM REGISTER
1
1
0
0
C
SDR
  SERIAL DATA REGISTER
1
1
0
1
D
ICR
  INTERRUPT CONTROL REGISTER
1
1
1
0
E
CRA
  CONTROL REGISTER A
1
1
1
1
F
CRB
  CONTROL REGISTER B

DATA BUS (DB0-DB7)

The eight data bus pins transfer information between the 6526 and the system data bus. These pins are high impedance inputs unless is low and and are high to read the device. During this read, the data bus output buffers are enabled, driving the data from the selected register onto the system data bus.

INTERRUPT REQUEST ()

is an open drain output normally connected to the processor interrupt input. An external pullup resistor holds the signal high, allowing multiple outputs to be connected together. The output is normally off (high impedance) and is activated low as indicated in the functional description.

RESET ()

A low on the pin resets all internal registers. The port pins are set as inputs and port registers to zero (although a read of the ports will return all highs because of passive pullups). The timer control registers are set to zero and the timer latches to all ones. All other registers are reset to zero.