6526 System Timing Characteristics

Symbol	Characteristic	1MHz		2MHz		Unit
		MIN.	MAX.	MIN.	MAX.
	Clock
TCYC	Cycle Time	1000	20,000	500	20,000	ns
TR, TF	Rise and Fall Time	-	25	-	25	ns
TCHW	Clock Pulse Width (High)	440	10,000	255	10,000	ns
TCLW	Clock Pulse Width (Low)	420	10,000	200	10,000	ns
	Write Cycle
TPD	Output Delay From	-	960	-	460	ns
TWCS	low while high	280	-	255	-	ns
TADS	Address Setup Time	58	-	20	-	ns
TADH	Address Hold Time	10	-	10	-	ns
TRWS	Setup Time	15	-	15	-	ns
TRWH	Hold Time	15	-	15	-	ns
TDS	Data Bus Setup Time	200	-	75	-	ns
TDH	Data Bus Hold Time	25	-	15	-	ns
	Read Cycle
TPS	Port Setup Time	300	-	150	-	ns
TWCS(2)	low while high	280	-	255	-	ns
TADS	Address Setup Time	58	-	20	-	ns
TADH	Address Hold Time	10	-	10	-	ns
TRWS	Setup Time	15	-	15	-	ns
TRWH	Hold Time	15	-	15	-	ns
TCO	to valid Data Out	-	240	150	-	ns
TACC	Data Access from RS3-RS0	-	550	-	275	ns
TCO(3)	Data Access from	-	320	-	150	ns
TDR	Data Release Time	50	-	25	-	ns

1. All timings are referenced from V_IL max and V_IH min on inputs and V_OL max and V_OH min on outputs.
2. T_WCS is measured from the later of high or low. must be low at least until the end of high.
3. T_CO is measured from the later of high or low. Valid data is available only after the later of T_ACC or T_CO.