6510/65816 Addressing mode: Zeropage/Direct Indirect Indexed -- (d),y

 (ADC,AND,CMP,EOR,LAX,LDA,ORA,SBC,STA)
 (2 bytes)  (5,6,7 and 8 cycles)

    +---------------+------------------+-----------------------+----------+
    |     Cycle     |   Address Bus    |       Data Bus        |Read/Write|
    +---------------+------------------+-----------------------+----------+
    |           1   |  PBR,PC          | Op Code               |    R     |
    |           2   |  PBR,PC+1        | Direct Offset         |    R     |
    |       (2) 2a  |  PBR,PC+1        | Internal Operation    |    R     |
    |           3   |  0,D+DO          | Absolute Address Low  |    R     |
    |           4   |  0,D+DO+1        | Absolute Address High |    R     |
    |       (4) 4a  |  DBR,AAH,AAL+YL  | Internal Operation    |    R     |
    |           5   |  DBR,AA+Y        | Data Low              |   R/W    |
    |       (1) 5a  |  DBR,AA+Y+1      | Data High             |   R/W    |
    +---------------+------------------+-----------------------+----------+
    (1) Add 1 cycle for M=0 or X=0 (i.e. 16 bit data).
    (2) Add 1 cycle for direct register low (DL) not equal 0.
    (4) Add 1 cycle for indexing across page boundaries, or write, or X=0.
        When X=1 or in the emulation mode, this cycle contains invalid
        addresses.

    See also: Abbreviations